1. Field of The Invention
The invention relates to the field of integrated circuit (IC) interconnect systems of the type in which solder bumps are evaporated onto selected locations on a semiconductor chip and, more particularly, to the addition of a thin layer of a metal such as palladium (Pd) or silver (Ag) onto the solder bumps to tailor the resultant melting temperature of bump interconnections made with low melting point solders.
2. Background Information
An electronic device may be formed of an assembly of integrated circuits (IC) chips interconnected to perform the particular device's required transfer of signals. The IC chips communicate with other chips in the device through an input/output (I/O) system of interconnects. A chip may be attached to a single chip module or a multi-chip module. These kinds of modules, which may be nothing more than chip holders or may themselves incorporate active devices, are known as a first level package. The modules are then generally attached to a printed circuit board (PCB) or card. Sometimes chips, without modules, are attached directly to the card. An assembly of chips and/or modules on a card is known as a second level package. These cards may be attached to another card, such as a motherboard, forming what is known as a third level package.
In many cases, the attachment of chips to modules, or modules to cards, is fixed by soldering the connections between the parts. Exposed conductors on one part are placed in close proximity to exposed conductors on another part with a quantity of solder, generally an alloy of tin (Sn) and lead (Pb). The solder is heated until the solder melts, a process called reflow. When the molten solder cools and solidifies, a fixed electrically conductive connection is formed.
In the course of making a final product, requiring a first level assembly process and a second level assembly process, for example, connecting chips to modules and modules to cards, the soldered connections may be exposed to heat sufficient to melt the solder several times. It is important that subsequent heatings do not destroy or significantly degrade the connections formed by earlier processes. This necessary durability can, in some cases, prove problematic.
A flip chip is an integrated circuit chip that is mounted on a substrate without conventional leads and pins. An active surface of the chip, i.e., a side with the input/output (I/O) connections, faces the substrate. A flip chip may be mounted to the substrate with any of a variety of interconnect materials and methods, such as isotropic and anisotropic conductive adhesives, fluxless solder bumps, wire interconnects, metal bumps, compliant bumps or pressure contacts. By eliminating the normal leads and pins found on other IC chips, flip chips generally provide the shortest possible leads, lowest inductance, highest frequency, best noise control, highest density, greatest number of I/O connections, smallest device footprint and the lowest profile.
A known technique for providing electrical interconnections between flip chips and a carrier, i.e. a module or a circuit board, is through the use of controlled-collapse chip connection (C4) technology, in which solder bumps are formed on one surface of the chip at chip interconnect points. These solder bumps are formed in a pattern or array on the chip surface, and a corresponding pattern or array of pads is formed on the carrier. The chip is "flipped" to bring the solder bumps into mating contact with the pads on the carrier. The entire assembly of chips and carrier is then subjected to heat above the melting temperature of the solder, which depending on the composition of the solder may be between 175.degree. C. and 320.degree. C. This causes the solder to reflow and wet the pads so that, upon cooling, a metallurgical bond is formed between the interconnect points and the pads on the carrier. This also insures a good electrical interconnection between the interconnect points and the pads.
Modern electronic packaging applications have continuously required the development of dense, small, high performance, and low cost module and card packages. To achieve these objectives, it may be desirable to incorporate high performance flip chip and controlled-collapse chip connection (C4) integrated circuit (IC) devices onto low cost organic chip carrier board materials such as fiberglass reinforced epoxy (FR4) composites, or other low cost board material systems.
However, most low cost carrier board materials generally cannot withstand prolonged temperature exposures above 230.degree. C. Consequently, both chips and carrier boards must have chip interconnect metallurgies and carrier surface finishes that support low temperature (&lt;230.degree. C.) soldering. Furthermore, the low temperature soldering must provide solder joint reliability with respect to the package design, materials selections, and during any first or second level assembly process exposures.
FIG. 3 depicts a conventional controlled collapse chip connection (C4) according to the prior art. Chip 100 includes an interface region 310 that connects to the chip's circuitry (not shown). A solder bump 320 is deposited on the interface region 310. The solder bump 320 is formed from a lead-rich alloy (97% lead, 3% tin by weight). Conventionally, a connection is formed between chip 100 and carrier substrate 300 by placing the solder bump 320 against the carrier pad 330. In this scenario, chip carrier materials that can withstand temperatures exceeding 270.degree. C.-300.degree. C. are required, because the entire structure must be heated to a temperature sufficient to melt the Pb-rich bump composition. The solder bump 320 wets when heated and forms a metallurgical bond to the carrier pad 330 upon cool down of the assembly and subsequent solidification of the bump-to-carrier pad solder joints.
When the assembly includes organic chip carrier materials, it is often necessary to perform the soldering at a lower temperature (175.degree. C.-230.degree. C.) to avoid damaging the organic materials. Low temperature processes are facilitated by using a carrier substrate 300 which includes a conventional copper carrier pad 330 that has been coated with an application of tin (Sn) or an eutectic composition tin-lead (Sn--Pb) alloy coating. The tin-lead alloy coating acts as a low melting point medium for attach, while a pure Tin coating provides the necessary metallurgical constituent to prompt a low melting point (eutectic) metallurgical reaction between the coating on pad 330, and the solder bump 320. In either case, a connection is formed between chip 100 and carrier substrate 300 by placing the solder bump 320 against the carrier pad 330. The entire structure is heated so that eutectic melting, wetting and subsequent bonding between the solder bump 320 and the coating on pad 330 occurs.
Chips possessing the conventional high lead (Pb) alloy bumps for low temperature solder interconnection processing can be made easier to use by applying metals such as tin (Sn) as caps on solder bumps 320, to eliminate need for a carrier pad 330 coating. For an example of capped bump structures, see U.S. Pat. No. 5,729,896. In this example, when a tin capped bump is placed into position on a carrier pad, a tin-lead liquid composition forms on the surface of the bump after heating to sufficient temperature, which subsequently wets to the carrier pad surface, and forms the solder joint between solder bump and carrier pad upon cool down and solidification.
However, in some manufacturing processes the joined connection is subjected to subsequent heatings, and because the melting point of the solder composition in the interconnection region has not significantly changed as a result of these previously known processes, further applications of heat must be carefully controlled or limited in number to avoid remelting or multiple remelting and solidification cycles. Otherwise, temperature excursions and associated phase transition sequences can potentially degrade the previously established interconnection. As the number of required heatings to manufacture a finished product grows, the need for precise control of the processes may become unmanageable.
Therefore, a need exists for a method of forming an electrical connection between a chip and a substrate, which allows the melting point of bump interconnections that are made with low melting point solders to be appropriately tailored.